Capacitor arrays or capacitor ladders are commonly used in the analog-to-digital converters (ADCs), digital-to-analog converters (DACs), switched capacitor filters and similar applications. A capacitor array includes a plurality of capacitors arranged in parallel. There are multiple requirements for a capacitor array, such as: (a) top plate to bottom plate capacitance of each capacitor in the capacitor array should be same; (b) minimum extension of the capacitor array in the X direction as it directly affects top level floor plan; and/or (c) a parasitic capacitance between top plate and bottom plate of each capacitor should be minimum.
In an ADC, top plates of the plurality of capacitors are coupled together, and also coupled to an amplifier. The bottom plate of each capacitor of the plurality of capacitors is coupled to at least one of a ground voltage and a reference voltage. A value of capacitance between top plate and bottom plate of each capacitor in the capacitor array is required to be of same value. When this condition is met, the capacitor array is ratio matched. A mismatch in the value of capacitance between top plate and bottom plate of a capacitor in the capacitor array, affects the DNL (differential non-linearity) and INL (integral non-linearity) of the ADC. Thus, whenever the plurality of capacitors in the capacitor array is not ratio matched, a single tone input to the ADC will result in harmonics at an output of the ADC.
Because of multiple factors, the plurality of capacitors is not ratio matched. These factors include, but not limited to, edge definition of the masking process, process variations and gradients across a chip. As technology is advancing at a rapid pace, the size of the capacitor is becoming smaller, and the parasitics due to bottom plate and top plate are becoming significant because of high integration.